pex 8605 , pci express gen 2 switch, 4 lanes, 4 ports ? plx technology, www.plxtech.com page 1 of 3 8/17/2011 , version 1.1 highlights ? PEX8605 general features o 4 - lane, 4 - port pcie gen2 switch ? integrate 5.0 gt/s serdes o 10 x 10mm 2 , 13 6 - pin a qfn package o typical power: 0.8 watts ? PEX8605 key featu res o standards compliant ? pci express base specification, r2. 1 (backwards compatible w/ pcie 1.0a/1.1) ? pci power management spe c, r1.2 ? microsoft windows 7 compliant ? dynamic serdes s peed control o high performance ? non - blocking switch fabr ic ? full line rate on all ports ? packet cut - thru with 250ns max packet l atency (x1 to x1) ? 256b max payload siz e o f lexible configuration ? ports configurable as x1, x2 ? regist ers configurable with strapping p ins, eeprom, i 2 c , or host software ? reference clock buffered output signals for down stream ports ? lane and polarity reversal ? compatible with pcie 1.0a pm o q uality of service (qos) ? eight traffic classes p er port ? round - robin source p ort arbitration ? relaxed pci ordering o re l iability, availability, serviceability ? visionpak ? ? per port performance monitoring ? per port payload & header counters ? s erdes eye capture ? error injection and loopback ? all ports hot plug capable thru i 2 c (hot - plug controller on every port) ? data path parity ? memory (ram) error correction signals ? inta# and fatal_err# ? advanced error reporting ? port status bits and gpio ava ilable ? per port error diagnostics ? jtag ac/dc boundary scan o power management ? wake#, beacon, vaux support the expresslane ? PEX8605 device offers pci express switching capabilit y enabling users to add scalable high bandwidth non - blocking interconnection to a wide variety of applications including control plane applications, consumer applications and embedded systems . the PEX8605 is well suited for fan - out and peer -to - peer applica tions . low packet latency & high performance the PEX8605 architecture supports packet cut - thru with a maximum latency of 250ns in x1 to x1 configuration . this, combined with low power consumption and non - blocking internal switch architecture, provides full line rate on all ports for low - power applications such as consumer and embedded . the low latency enables applications to achieve high throughput and pe rformance. in addition to low latency, the device supports a max payload size of 256 bytes . data integrity the PEX8605 provides end -to - end crc protection (ecrc) and poison bit support to enable designs that require guaranteed error - free packets . plx also supports data path parity and memory (ram) error correction as packets pass through the switch. power management and clock buffering the PEX8605 supports the following power management states: l0, l0s, l1, l2/l3 ready, l2 and l3. moreover, the PEX8605 supports vaux along with the external signal wake# and the in - band beacon for the pcie endpoints to use to inform the system host to exit the low power savings mode. the pex 8605 supports three pairs of pci express - compliant, 100mhz, buffered hcsl outpu t clocks, one pair for each downstream port of the switch. each clock output pair can be disabled by software or serial eeprom when not in use, for additional power savings. this feature greatly reduces system bom cost by eliminating the need for extra cl ock buffers on the pcb. interoperability the PEX8605 is designed to be fully compliant with the pci express base specification r2. 1 and is backwards compatible to pci express base specification r1.1 and r1.0a. additionally each port supports auto - negotiation and polarity reversal . furthermore, the PEX8605 is designed for microsoft windows 7 compliance. all plx switches undergo thorough interoperability testing in plx?s interoperability lab and compliance testing at the pci - sig plug - fest to ens ure compatibility with pci express devices in the market. device operation configuration flexibility the PEX8605 provides several ways to configure its operations. the device can be configured through strapping pins, i 2 c interface, cpu configuration cycles and/or an optional serial eeprom. this allows for easy debug during the development phase and functional monitoring during the operation phase .
pex 8605 , pci express gen 2 switch, 4 lanes, 4 ports ? plx technology, www.plxtech.com page 2 of 3 8/17/2011 , version 1.1 flexible port configurations the PEX8605 flexible architecture supports a number of port configurations as required by the target applications as shown in figure 1 below. figure 1. port configurations serdes power and signal management the PEX8605 provides low power capability that is fully compliant with the pci express power management specification. in addition, the serdes physical links can be turned off when unused for even lower power. the PEX8605 supports software control of the serdes outputs to allow optimization of power and signal strength in a system. the plx serdes implementation supports four levels of power ? off, low, typical, and high. the serdes block also supports loop - back modes and a dvanced reporting of error conditions , which enables efficient debug and management of the entire system. port arbitration and qos the PEX8605 switch supports hardware fixed round - robin ingress port arbitration. the PEX8605 also supports eight traffic cl asses (tcs) as defined in the pcie specification . applications suitable for fan - out, consumer, control plane applications, and embedded systems , PEX8605 is suited for a wide variety of form factors and applications. fan- out the PEX8605 switch, with its flexible configurations, allows user specific tuning to a variety of host - centric as well as peer - to - peer applications . figure 2. fan - in/out usage figure 2 shows a typical fan - out design, where the processor provides a pci express link that needs to be fanned into a larger number of smaller ports for a variety of i/o functions, each with different bandwidth requirements. multi - function printer with its small footprint, the PEX8605 is ideal for consumer applications. figure 3 shows a multi - function printer block diagram. the four ports in the PEX8605 provide connectivity between the processor to up to three peripherals each via an x1 connection. in this usage model, the PEX8605 provides connectivity to the processor as well as to the v arious asics. figure 3. printer block diagram digital tv tuner an example of a digital tv tuner is shown in figure 4. in this example, the integrated soc has a single pcie connection. the PEX8605 is used to provide connection to the usb 3.0 endpoint, a gigabit ethernet controller and a 3d graphics engine which are used to connect to other consumer peripherals, to a high speed home network and provide advanced graphics respectively. figure 4. digital tv tuner fan - in/out usage b andwidth bridge there are four pcie lanes available in the PEX8605 . each one ca n represent an individual port or alternatively two can be joined to form a x2 port. a x2 port can provide double the bandwidth of a x1 por t when all lanes are operating at the sa me data rates (all at 2.5gt/s or 5.0gt/s). in some instances, the need to match the bandwidth between devices running at pex 8605 x1 x1 x1 x1 pex 8605 x1 x2 x1 cpu pex 8605 pcie pcie pcie x1 x1 x1 x1 2.5 &5 gt/s system x1 pex 8605 processor asic asic eth scanner marking engine x1 x1 x1 x1 soc gbe x1 x1 pex 8605 usb3.0 3d engine x1
PEX8605 , pci express gen 2 switch, 4 lanes, 4 ports ? plx technology, www.plxtech.com page 3 of 3 8/17/2011 , version 1.1 different data rates (2.5gt/s vs 5.0gt/s) is required to sust ain the performance of the faster device. figure 5 provides an example where the PEX8605 is configured as x2, x1, x1. i n this example, the x2 link is running at the lower data rate (2.5gt/s) while a single x1 port is running at the higher data rate (5.0 gt/s). in this usage model, the PEX8605 acts as a bridge between gen 1 and gen 2 devices allowing the faster devic e to operate at its full bandwidth capabilities. figure 5. gen 1 to gen 2 bandwidth bridge s oftware usage model from a system model viewpoint, each pci express port is a virtual pci to pci bridge device and has its own set of pci express configuration registers. it is through the upstrea m port that the bios or host can configure the other ports using standard pci enumeration. the virtual pci - to - pci bridges within the PEX8605 are compliant to the pci and pci exp ress system models. the configuration space registers (csrs) in a virtual primary/secondary pci - to - pci bridge are accessible by type 0 configuration cycles through the virtual primary bus i nterface (matching bus number, device number, and function n umber). in terrupt sources/events the PEX8605 supports the intx in terrupt message type (compatible with pci 2.3 interrupt signals) or message sign aled interrupts (msi) when e nabled. interrupts/messages are generated by PEX8605 for hot - plug events, doorbell interru pts, baseline error reporting, and advanced error reporting. d evelopment tools plx offers hardware and s oftware tools to enable rapid customer design activity. thes e tools consist of a hardwa re module ( PEX8605 rdk), hardware documentation (available at www.plxtech.com ) , and a software development kit (also available at www.plxtech.com ). expressl ane PEX8605 rdk the PEX8605 rdk is a hardware module containing the PEX8605 which plugs right into your system. the PEX8605 rdk can be used to test and validate customer software, or used as an evaluation vehicle for PEX8605 features and benefits. the pex rdk provides everything that a user needs to get their hardware and software development started. figure 6. PEX8605 rapid development kit s oftware development kit (sdk) plx?s software development kit is availab le for download at www.plxtech.com/sdk . the software development kit includes drivers, source code, and interfaces to aid in configuring and debugging the PEX8605 . both performance pak and vision pak are supported by plx?s rdk and sdk, the industry?s most advanced hardware - and software - development kits. product ordering information part number description pex 8605 - aa50ni g 4 lane, 4 port pci express gen 2.0 switch, pb - free (10x10mm 2 PEX8605 - aa rdk aqfn) pex 8605 rapid development kit + cm108 (one x1 upstream port, three x1 downstream ports) pex 8605 - aa - 2u1d rdk pex 8605 rapid development kit + cm107 (one x2 upstream port, two x1 downstream ports) plx technology, inc. all rights reserved. plx, the plx logo, expresslane, read pacing , dual cast , performancepak and visionpak are trademarks of plx technology, inc. all other product names that appear in this material are for identification purposes only and are acknowledged to be trade marks or registered trademarks of their respective companies. information supplied by plx is believed to be accurate and reliable, but plx assumes no responsibility for any errors that may appear in this material. plx reserves the right, without notice, to make changes in product design or specification. visit www.plxtech.com for more information. pex 8605 gen 2 gen 1 x2 x1 bandwidth bridge 2.5 gt/s 5.0 gt/s pex8518 eeprom dip switch for cfg. jtag header refclk hd power connector x1 perst# p ort 2 ? x1 p ort 3 ? x1 manual reset 1 2 v -t o - 1 v n o n - i s o c o n v e r t e r (upstream port) lane status leds p ort 1 ? x1 reset ckt. i2c pex 8518 pex 8605
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